1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits using MOS transistors has been increasing. With the increasing degree of integration, the size of MOS transistors used in integrated circuits has been decreased to nano-scale dimensions. Such a decrease in the size of MOS transistors causes difficulty in suppressing leak currents, which poses a problem in that it is hard to reduce the area occupied by the circuits because of the requirements of the secure retention of necessary currents. To address the problem, a surrounding gate transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged vertically with respect to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer has been proposed (e.g., refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
In an existing method for producing an SGT, a silicon pillar on which a nitride film hard mask is formed in a pillar shape is formed, a diffusion layer is formed in a lower portion of the silicon pillar, a gate material is then deposited, the gate material is then planarized and etched back, and an insulating film sidewall is formed on the side wall of the silicon pillar and the nitride film hard mask. Subsequently, a resist pattern for forming a gate line is formed, the gate material is etched, the nitride film hard mask is then removed, and a diffusion layer is formed in an upper portion of the silicon pillar (e.g., refer to Japanese Unexamined Patent Application Publication No. 2009-182317).
In such a method, when the distance between the silicon pillars is decreased, a thick gate material needs to be deposited between the silicon pillars and thus holes called voids may be formed between the silicon pillars. If voids are formed, holes are made in the gate material after the etching back. When an insulating film is then deposited to form an insulating film sidewall, the insulating film is deposited in the voids. This causes difficulty in gate material processing.
In view of the foregoing, it has been disclosed that a silicon pillar is formed, a gate oxide film is then formed, a thin polysilicon is deposited, a resist that covers an upper portion of the silicon pillar and is used to form a gate line is then formed, a gate line is etched, a thick oxide film is then deposited, the upper portion of the silicon pillar is caused to be exposed, the thin polysilicon on the upper portion of the silicon pillar is removed, and the thick oxide film is removed by wet etching (e.g., refer to B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. D. Lo, and D. L. Kwong, “Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET”, IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp 791-794).
However, a method in which a metal is used for gate electrodes is not described. In addition, a resist that covers an upper portion of the silicon pillar and is used to form a gate line needs to be formed. Therefore, the upper portion of the silicon pillar needs to be covered and thus such a method is not performed in a self-aligned process.